1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing and operating the same, and more particularly, to a multi-bit memory device having resistive material layers as a storage node, and methods of manufacturing and operating the same.
2. Description of the Related Art
There are two types of memory: volatile memory, that loses the stored data when power is turned off, and non-volatile memory, that does not require power to retain its contents. With the advancement in Internet technology and increasing popularity of mobile communication devices, increasing attention is being directed toward non-volatile memory devices. While flash memory is now commonly used as a non-volatile memory, next-generation non-volatile memories continue to be introduced, including ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), silicon-oxide-nitride-oxide-silicon (SONOS) memory, resistive RAM (RRAM), and phase change RAM (PRAM), some of which are being used for limited commercial applications.
RRAM or PRAM differs from other non-volatile memories in that it uses a resistor as a memory node. A storage node in a PRAM includes a phase change layer that changes between an amorphous and a crystalline phase according to a given condition. The phase change layer exhibits high resistance in the amorphous state and low resistance in the crystalline state. This resistance variation in the phase change layer allows the PRAM to write and read data bits.
FIG. 1 shows a conventional PRAM having a resistive material layer as a storage node. Referring to FIG. 1, the conventional PRAM includes a field-effect transistor (‘transistor’) that is formed on a semiconductor substrate 10 and has a source 12, a drain 14, and a gate stack 16 containing a gate electrode. The transistor is covered by a first interlayer insulating layer 18. The first interlayer insulating layer 18 includes a first conductive plug 20 that penetrates through the first interlayer insulating layer 18 and is connected to the drain 14. The first conductive plug 20 is used as a lower electrode. A germanium-antimony-tellurium (GeSbTe, also referred to as ‘GST’) layer 22 is formed on the first interlayer insulating layer 18 to cover the top surface of the first conductive plug 20. The GST layer 22 is a phase change layer and is used as a memory node. An upper electrode 24 is formed on the GST layer 22, both of which are covered by a second interlayer insulating layer 26. A contact hole 28 which exposes a source 12 is formed in the first and second interlayer insulating layers 18 and 26 and filled with a second conductive plug 30. A bit line 32 is formed on the second interlayer insulating layer 26 and coupled to the top surface of the second conductive plug 30.
The operation of the conventional PRAM will now be described briefly.
When a phase change current is applied to the GST layer 22, a portion of the GST layer 22 changes from a crystalline state to an amorphous state. The resistance of the GST layer 22 increases after the phase change current is applied. Because the phase change current changes the resistance of the GST layer 22, a data bit 1 is considered to have been written to the GST layer 22 when the GST layer 22 has high resistance after the phase change current is applied. On the other hand, when the GST layer 22 has low resistance before the phase change current is applied, a data bit 0 is considered to have been written to the GST layer 22.
In the conventional PRAM, the state of the GST layer 22 varies according to the current applied. However, the phase change current applied to change a portion of the GST layer 22 to the amorphous state poses a major challenge to improving the characteristics of PRAM. The advancement of semiconductor manufacturing technology makes it technically possible to reduce the size of PRAM by reducing the size of storage node and transistor. However, as the transistor becomes smaller, its current supply capability decreases. Thus, when the current allowed through the transistor is less than that needed to cause the phase change of the GST layer 22, the PRAM is difficult to operate. This results in a restriction to the integration density of PRAM. Another drawback of the conventional PRAM is that it cannot write more than 2-bit data.